This invention relates to routers used for routing messages between a local area network (LAN) and one or more wide area networks (WANs) and more particularly to a router architecture integrated onto a single silicon chip that is adaptable to a wide variety of network configurations.
A router is essentially a computer dedicated to the task of routing messages between different network protocols and between different networks having similar protocols. The router must contain the necessary input and output connections for linking different network systems together. Routers also have an internal computer architecture and associated control for converting data packets between different network protocols. For example, Ethernet is a widely-used standard for LANs that allows data transfer rates of 10 million bits per second (Mbps). Ethernet can be used to implement bus architecture networks. In contrast, WANs typically implement point-to-point connections and transfer data packets at rates below 1 Mbps.
A variety of different routers and associated router architectures have been developed to support different network configurations. Routers typically include multiple circuit boards connected together in a chassis which typically has a size comparable with the processing box of a personal computer. The cabinet, circuit boards, interface circuitry, etc., used to build a router are expensive and require a substantial amount of assembly time. To reduce the physical size and cost of routers and the amount of time required for assembly, it would be necessary to integrate many of the different router functions onto the same circuit board or processing chip. However, due to the variety of different network configurations and protocols used in different network systems, current router architectures are not capable of adequately supporting a wide variety of network configurations, network protocols and other peripheral devices without considerable cost. For example, routers are typically designed to operate with a given combination of external serial and time division multiplexed data lines. The router may not support the new network configuration if the format of the data stream transmitted over the lines changes or a different combination of external network lines are used.
The time required for a router to convert and route data packets into different network protocols and between different networks depends upon how efficiently data packets are transferred between different router processing elements. However, different amounts of data can be transmitted to the router at any given time from any one of the connected networks. The internal bus architecture in current router architectures have a dedicated bandwidth allocation scheme for processing data packets from each external network connection. However, dedicated bandwidth allocation does not utilize internal bus transactions efficiently for network data packets that may be received or transmitted at variable data rates from each connected network. Thus, router performance can degrade for certain network processing conditions.
Accordingly, a need remains for a router architecture integrated onto a single silicon chip that is adaptable to a wide variety of different network systems and peripheral interfaces while at the same time being adaptable to changing data processing requirements and reducing the overall cost of the router.